FPGA implementation of floating-point complex matrix inversion based on GAUSS-JORDAN elimination
This work presents the architecture of an optimized complex matrix inversion using GAUSS-JORDAN elimination (GJ-elimination) on FPGA with single precision floating-point representation to be used in MIMO-OFDM receiver. This module consists of single precision floating point arithmetic components and control unit which perform the GJ-elimination algorithm. The proposed architecture performs the GJ-elimination for complex matrix element by element. Only critical arithmetic operations are calculated to get the needed values without performing all the arithmetic operations of the GJ-elimination algorithm. This results in a reduced hardware resources and execution time. © 2013 IEEE.
This conference paper is not available at CUD collection. The version of scholarly record of this conference paper is published in 2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) (2013), available online at: https://doi.org/10.1109/CCECE.2013.6567785.
Matrix inversion, MIMO, OFDM, Arithmetic operations, Complex matrices, FPGA implementations, Gauss-Jordan elimination, Hardware resources, Proposed architectures, Single precision, Digital arithmetic, Field programmable gate arrays (FPGA), Orthogonal frequency division multiplexing, Computer architecture
Moussa, S., Abdel Razik, A. M., Dahmane, A. O., & Hamam, H. (2013). FPGA implementation of floating-point complex matrix inversion based on GAUSS-JORDAN elimination. In Canadian Conference on Electrical and Computer Engineering. https://doi.org/10.1109/CCECE.2013.6567785